In recent years, reproducing apparatus for optical discs such as digital video discs (hereinafter referred to DVD) which carry optical record information of digitally compressed video signals or data handled in personal computers, etc. have been proposed and efforts are intensively concentrated to bring the commercial stage. The DVDs feature a recording density far higher than conventional compact discs so that movies exceeding two hours can be recorded on one side of a single disc having the same 12 cm diameter as compact discs.
To accurately reproduce information from such a recording medium, an accurate and precise tracking servo is required. Therefore, it becomes necessary to precisely generate a tracking error signal from pickup signals. In the DVD system, a method of detecting a tracking error by receiving reflected lights from a beam spot irradiated from a laser using a photo-detector divided into four diagonally arranged photoreceptive cells. The outputs outputs of two diagonal cells are then summed so as to detect a phase error between the outputs as the tracking error. Such a method is considered the best from the nature standard of the DVD system. This method is based on the principle that a phase error occurs between the two sets of the sums of the diagonal components by a tracking error. It is then called "phase error-based tracking error generation".
A Japanese laid-open Application Tokkai-Sho 58(1983)-150144 discloses a tracking error generator embodying the system, while a Japanese published Application Tokko-Hei 05(1993)-80053 discloses a further improvement of the sort of the tracking error generator. In a practical configuration of the tracking error signal generators for DVDs having a very high record density, it is required to detect a phase error at a high speed and a high accuracy for every pulse. Thus such a tracking error signal generator faces some very difficult problems. For instance, the Japanese published Application Tokko-Hei 05(1993)-80053 discloses a tracking error signal generator, as shown in FIG. 6, which sequentially integrates phase comparison results for every pulse so as to eliminate an affect caused by any defective waveform correspondency occurring in the combination of pulse signals.
Now, the operation of the prior art circuit, as illustrated in FIG. 6, will be described in reference to a waveform diagram, as shown in FIG. 7. Two sets of diagonal sum signals A+C and B+D obtained from photodetectors having four photoreceptive cells A, B, C and D are assumed to have a phase error therebetween in response to an amount of the tracking error, as shown in FIG. 7. An input pulse signal 1 is a binary rectangular pulse signal obtained by wave-shaping the diagonal sum signal A+C, while another input pulse signal 2 is another binary rectangular pulse signal obtained by wave-shaping the other diagonal sum signal B+D. A reference polarity (RP) signal is produced from the input pulse signals 1 and 2 as that it has a trailing edge which arises at the leading edge of a delayed one of the corresponding pulses in the input pulse signals 1 and 2, and a trailing edge which arises at the trailing edge of a delayed one of the corresponding pulses in the input pulse signals 1 and 2.
Those three input signals 1, 2 and RP are supplied to a phase comparator 61, as shown in FIG. 6. The phase comparator 61 operates EX-OR (Exclusive-OR) operations on a first combination of the input pulse signal 1 and the reference polarity signal RP, and a second combination of the input pulse signal 2 and the reference polarity signal RP. In the phase comparator 61, the EX-OR outputs are further converted into current signals through resistors R4 and R5 and then charged into a front stage capacitor C1. If the input pulse signal 1 advances in phase to the input pulse signal 2, the EX-OR output associated with the input pulse signal 1 takes the High level for the periods of the phase error (i.e., between the leading edges of the input pulse signal 1 and the reference polarity signal RP and the trailing edges of the input pulse signal 1 and the reference polarity signal RP). A current It then flows through the resistor 4 to charge the capacitor C1 for the duration of the high level. On the other hand, if the input pulse signal 1 delays in phase than the input pulse signal 2, the EX-OR output associated with the input pulse signal 2 takes the high level for the period of the phase error (i.e., between the leading edges of the input pulse signal 2 and the reference polarity signal RP and the trailing edges of the input pulse signal 2 and the reference polarity signal RP). Another current I2 then flows through the resistor R5 to charge the capacitor C1 in the reverse direction.
During the above operations, switches SW1 and SW2 are kept open. A duration from an instance when corresponding two edges of the input pulses have arrived to another instance when either one of corresponding edges of following pulses arrives, the switch SW1 is kept ON, as shown in FIG. 7. The condition keeping the switch SW1 ON is determined by a switch controller 62 which is configured in a logic circuit. When the switch SW1 is kept ON, the capacitor C1 is coupled to an integrator 63 which is comprised of an operational amplifier OP and a capacitor C2. The operational amplifier OP so operates that the voltage between inputs becomes zero.
The electric charge charged in the capacitor C1, having a charge amount in proportion to the phase error, is then transferred to the capacitor C2 (see current 13). Thus the charge across the capacitor C1 has been automatically reset to zero before arriving of next input pulses by the operational amplifier operation. The electric charge is transferred at a speed limited by the bandwidth of the operational amplifier. In this charge transfer operation, a relatively large rush of current flows. Then resistors R6 and R7 are inserted along the current paths for suppressing the rush currents below their reasonable current levels.
Thus, the electric charge charged in the capacitor C1 for every input pulse is sequentially transferred to the rear stage capacitor C2, thus the electric charges are integrated in the capacitor C2. A voltage having a mean value corresponding to the phase error is then produced at the output of the integrator 63. The voltage output is thus utilized as a tracking error signal. When any defective waveform correspondence occurs in the combination of the inputs I1 and I2, a defective waveform correspondency detector 64 detects the defective waveform correspondency to close the switch SW3 for resetting the charge of the capacitor C1. Thus the tracking error signal produced from the integrator 63 is shut out from the affection of the defective waveform correspondency. As shown in FIG. 7, in the illustrative diagonal sum signal A+C, its second peak fails to reach the threshold level for binarization. So that, a binarized rectangular pulse signal of the corresponding second peak of the other diagonal sum signal B+D results in an isolated pulse.
In this case, the switch controller 62 does not close the switch SW1 so that the electric charge of the capacitor C1 fails to be transferred. While the switch SW3 is turned ON by a defective waveform correspondency detector 64 immediately after the trailing edge of the input pulse signal 2 to short-circuit both ends of the front stage capacitor C1. Thus in the occurrence of the defective waveform correspondency the charge of the front stage capacitor C1 is reset without being transferred to the rear stage capacitor C2.
However, the prior art circuit, as shown in FIG. 6, has the disadvantage that it is difficult to adapt to the high speed operation required in a DVD system, and it can not accurately operate in such high speed operation systems. Because such processings require high speed performance, low offset and low S/N ratios, the IC is implemented using a bipolar process. The prior art circuit, as shown in FIG. 6, however has several problems in attempting its IC integration by the bipolar process.
First, it is difficult to realize a bidirectional current ON/OFF switch for the first switch SW1. To realize such a bidirectional current switch, requires a bidirectional current switch function by a diode bridge, as shown in FIG. 8, which turns ON/OFF in response to the activation/deactivation of bias currents.
In such a bidirectional current switch, a bias current source IS1 associated with a power source Vcc, is constructed by PNP transistors, while another bias current source IS2 associated with a ground source is constructed by NPN transistors. The PNP transistors and the NPN transistors are different in their response characteristics with each other. Thus, the bias current sources using transistors of different conductivity types can not be completely turned ON/OFF at the same time. Further, the current capacities of the bias current sources are required to be larger than the maximum current which flows for the transfer of the electric charge. The capacity of the bias current sources can not be reduced.
Accordingly, in the prior art phase error detector, using the bidirectional current switch, as shown in FIG. 8, a large offset current flows into the front and rear stage capacitors C1 and C2, provided that the ON/OFF response times of the PNP and NPN transistors are small, thereby deteriorating the accuracy of the phase error signal generation. In practice, the DVD systems require that the the phase error offset be suppressed below several nsecs. Thus the difference of the ON/OFF timing must be reduced below such several nsecs. However at present there is no means to sufficiently reduce the difference. Further, a current continues to flow for a while after the charge transfer has completed at the time that the bias current sources are turned ON. Thus, the difference of the currents of the bias current sources flows into the integrator 63 still after the completion of the charge transfer, thereby causing inaccuracy of the phase error signal generation.
In this case too, there arises the serious problem that it is difficult to balance the accuracies of both bias current sources since they are made of the different conductivity type transistors. When an almost correct tracking is carried out, the phase error signal output approaches zero. In this state, the error detecting operation tine is shortened for a very short portion within a duration until next pulse, while the ON state of the switch SW1 for transferring the electric charge extends for almost the entire portion of the duration. Provided the amount of current offset is small, a considerably large error occurs in the generated error signal. In place of the diode-bridge, there is another approach of realizing a bidirectional current switch function by a saturation switch, as shown in FIG. 9. In this case, the saturation switch still has problems that it causes a large voltage offset and a slow operation. Thus the case of the saturation switch still has a considerably large error.
Furthermore, the prior art circuit, as shown in FIG. 6, has the problem that the operational amplifier OP do not have the characteristics necessary to achieve high-speed operations. In general, an output stage of the operational amplifier is constructed in a push-pull circuit configuration comprising PNP and NPN transistors. In this push-pull configuration, an active side of the transistors changes depending on whether the transfer of the electric charge charges or discharges the rear stage capacitor C2. In normal bipolar ICs, PNP transistors have a lateral structure while NPN transistors have a vertical structure, thus there exists remarkable difference between them in their high speed operation characteristics according to the structural difference.
Thus, a large difference occurs between the speeds of the charging operation and discharging operation. This difference of the operating speeds further results in a difference of advance and delay of phases. Viewed from a phase error characteristic curve, there arises a difference in the amounts of tilting of the curves in opposite sides in relation to a zero phase origin point. In case that the output stage has an NPN emitter-follower configuration, as well as the case of the push-pull type output stage, the difference of the operating speeds results in a charging operation to the emitter electrode of the NPN transistor and a constant-current discharging from the collector electrode of the NPN transistor. The charging and the constant-current discharging still result in a large difference of characteristics between the advance and delay of phases. In addition, an offset between two input currents is taken into account as a factor of causing the difference.
In case of a conventional phase error signal generator which transfers electric charge using an operational amplifier and an ON/OFF switch, there was such problems that it would not be possible to obtain a sufficient performance for such discs as DVD requiring operations in both high accuracy and high speed.